For some applications, such as high frequency or radio frequency (“RF”) applications, it may be desirable to form integrated passive devices using semiconductor processing technology or it may be desirable to integrate passive devices such as inductors and/or capacitors together with active devices such as transistors using conductive silicon substrates. However, passive devices may have relatively low quality factors (“Qs”) when these passive devices are formed on, or in relatively close proximity to, the conductive silicon substrate. In addition, due to parasitic capacitive coupling between these passive devices and the conductive silicon substrate, the frequency of operation of the integrated devices is reduced. Electrically conductive interconnects or busses may be used to electrically couple different devices within the die and external to the die. The frequency of operation may also be reduced by parasitic capacitive coupling between the interconnects and the conductive silicon substrate.
Further, it may be desirable to physically and electrically isolate regions of a semiconductor substrate from each other. Additionally, some semiconductor devices, such as power transistors, provide relatively high power output, which may be desirable in some RF, industrial, and medical applications. Power transistor designers are continually seeking ways to efficiently increase power output by varying the output voltage and current characteristics of a power transistor. For example, it may be desirable to have a power transistor that has an increased breakdown voltage to enable the power transistor to operate at a relatively higher voltage and provide a relatively higher power output.
Accordingly, it is desirable to have improved semiconductor structures, and methods to make these structures, that may provide for reduced parasitic capacitances, relatively higher frequencies of operation, relatively higher breakdown voltages, relatively higher quality factor passive devices, improved isolation, or combinations thereof.
For simplicity of illustration and ease of understanding, elements in the various figures are not necessarily drawn to scale, unless explicitly so stated. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements. In some instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present disclosure. The following detailed description is merely exemplary in nature and is not intended to limit the disclosure of this document and uses of the disclosed embodiments. Furthermore, there is no intention that the appended claims be limited by the title, technical field, background, or abstract.